Intel 11th Generation CPU Instruction Sets available on Hyper-V Ubuntu guest

In the past post Intel 11th Generation CPU Instructions Available on Hyper-V, it has shown the information about CPU instruction sets available on Windows 11 Pro host and Windows Guest VM. But how about Linux guest? It will be shown on below, but please note due to being unable to use CoreInfo on Ubuntu guest, we just use the <em>lscpu</em> command to display the instruction sets.

Architecture:             x86_64
  CPU op-mode(s):         32-bit, 64-bit
  Address sizes:          39 bits physical, 48 bits virtual
  Byte Order:             Little Endian
CPU(s):                   4
  On-line CPU(s) list:    0-3
Vendor ID:                GenuineIntel
  Model name:             11th Gen Intel(R) Core(TM) i5-1135G7 @ 2.40GHz
    CPU family:           6
    Model:                140
    Thread(s) per core:   2
    Core(s) per socket:   2
    Socket(s):            1
    Stepping:             1
    BogoMIPS:             4838.39
    Flags:                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse s
                          se2 ss ht syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology tsc_reliable nonst
                          op_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic
                          movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand hypervisor lahf_lm abm 3dnowprefetch
                           ssbd ibrs ibpb stibp ibrs_enhanced fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid avx51
                          2f avx512dq rdseed adx smap avx512ifma clflushopt clwb avx512cd sha_ni avx512bw avx512vl xsave
                          opt xsavec xgetbv1 xsaves user_shstk avx512vbmi umip avx512_vbmi2 gfni vaes vpclmulqdq avx512_
                          vnni avx512_bitalg avx512_vpopcntdq rdpid movdiri movdir64b fsrm avx512_vp2intersect md_clear
                          ibt flush_l1d arch_capabilities
Virtualization features:
  Hypervisor vendor:      Microsoft
  Virtualization type:    full

And due to being unable to do direct comparison, we will use AI to help do the comparison. Please note AI can make mistakes, the comparison below only for learning purposes. For the AI comparison also, we can see the CPU Instructions available in Ubuntu guest are almost similar with Windows guest as per last post.

AI Comparison

Here's a comparison of the CPU instructions from List 1 (Windows CoreInfo) and List 2 (Ubuntu lscpu).

List 1 CPU Instructions Not Directly Present in List 2

Based on the provided lists and common lscpu flag conventions, the following List 1 instructions do not have a direct corresponding flag in List 2. Some of these may refer to broader technologies, specific MSRs, or hardware features not typically detailed as individual flags by lscpu:

1. MONITOR: Refers to MONITOR/MWAIT instructions. While often present on modern CPUs, lscpu may not always list a specific flag for it.
2. DTES64: "Can write history of 64-bit branch addresses" (Debug Trace ETM Subsystem 64-bit). Specific debug capabilities like this are often not itemized in lscpu flags.
3. DS: "Implements memory-resident debug buffer" (Debug Store). Similar to DTES64, specific debug features may not have individual flags in lscpu.
4. PDCM: "Supports Performance Capabilities MSR". lscpu typically doesn't list flags for specific MSRs by such names.
5. xTPR: "Supports disabling task priority messages". While related to APIC, a specific xtpr or xtpr_update_control flag is not in List 2.
6. EIST: "Supports Enhanced Intel SpeedStep". lscpu might show est on older systems or related flags like hwp (Hardware P-states) but not typically "EIST" by name. Power management features are often handled differently.
7. ACPI: "Implements MSR for power management". ACPI is a broad standard, not a specific CPU instruction flag that lscpu would list.
8. TM: "Implements thermal monitor circuitry" (Thermal Monitor 1). Basic thermal monitoring is standard; specific flags like tm or thermal_monitor are not in this List 2.
9. TM2: "Implements Thermal Monitor 2 control". Similar to TM, not present as a flag in List 2.
10. PBE: "Supports use of FERR#/PBE# pin" (Pending Break Enable). This refers to a specific hardware signaling feature not typically listed as an lscpu CPU flag.

Mapping Table of List 1 to List 2 Instructions

The following table maps each instruction from List 1 to its corresponding instruction or feature in List 2. Notes are provided where names or groupings differ but refer to similar functionalities.

List 1 Instruction (CoreInfo)	List 2 Instruction/Note (lscpu)
HTT	ht (Hyperthreading)
CET	ibt, user_shstk (Control Flow Enforcement Technology components: Indirect Branch Tracking and User-mode Shadow Stack)
User CET	user_shstk (User-mode Shadow Stack, a component of User-mode CET)
HYPERVISOR	hypervisor
X64	lm (Long Mode, indicates 64-bit support)
NX	nx (No-eXecute bit)
SMEP	smep (Supervisor Mode Execution Prevention)
SMAP	smap (Supervisor Mode Access Prevention)
PAGE1GB	pdpe1gb (1GB Page Support)
PAE	pae (Physical Address Extension)
PAT	pat (Page Attribute Table)
PSE	pse (Page Size Extension)
PSE36	pse36 (36-bit Page Size Extension)
PGE	pge (Page Global Enable)
SS	ss (Self-Snoop)
VME	vme (Virtual Mode Extensions)
RDWRFSGSBASE	fsgsbase (FS/GS Base access instructions)
FPU	fpu (Floating Point Unit)
MMX	mmx
SSE	sse (Streaming SIMD Extensions)
SSE2	sse2 (Streaming SIMD Extensions 2)
SSE3	pni (Prescott New Instructions, an alternative name for SSE3)
SSSE3	ssse3 (Supplemental Streaming SIMD Extensions 3)
SSE4.1	sse4_1 (Streaming SIMD Extensions 4.1)
SSE4.2	sse4_2 (Streaming SIMD Extensions 4.2)
AES	aes (AES New Instructions)
AVX	avx (Advanced Vector Extensions)
AVX2	avx2 (Advanced Vector Extensions 2)
AVX-512-F	avx512f (AVX-512 Foundation)
AVX-512-DQ	avx512dq (AVX-512 Doubleword and Quadword Instructions)
AVX-512-IFAMA	avx512ifma (AVX-512 Integer Fused Multiply-Add)
AVX-512-CD	avx512cd (AVX-512 Conflict Detection Instructions)
AVX-512-BW	avx512bw (AVX-512 Byte and Word Instructions)
AVX-512-VL	avx512vl (AVX-512 Vector Length Extensions)
FMA	fma (Fused Multiply-Add)
MSR	msr (Model Specific Registers RDMSR/WRMSR)
MTRR	mtrr (Memory Type Range Registers)
XSAVE	xsave (XSAVE/XRSTOR instructions). List 2 also has xsaveopt, xsavec, xsaves.
OSXSAVE	xgetbv1 (Indicates OS support for XSAVE features via XGETBV[1])
RDRAND	rdrand (RDRAND instruction)
RDSEED	rdseed (RDSEED instruction)
CMOV	cmov (Conditional Move instruction)
CLFSH	clflush (CLFLUSH instruction). List 2 also has clflushopt, clwb.
CX8	cx8 (CMPXCHG8B instruction)
CX16	cx16 (CMPXCHG16B instruction)
BMI1	bmi1 (Bit Manipulation Instructions 1)
BMI2	bmi2 (Bit Manipulation Instructions 2)
ADX	adx (ADCX/ADOX instructions)
F16C	f16c (16-bit Floating-Point conversion instructions)
FXSR	fxsr (FXSAVE/FXRSTOR instructions)
MONITOR	Not directly listed in List 2.
MOVBE	movbe (Move Big-Endian instruction)
ERMSB	erms (Enhanced REP MOVSB/STOSB)
PCLMULDQ	pclmulqdq (Carry-Less Multiplication instruction)
POPCNT	popcnt (Population Count instruction)
LZCNT	abm (Advanced Bit Manipulation, includes LZCNT). Note: popcnt is also part of abm but listed separately in both.
SEP	sep (SYSENTER/SYSEXIT, Fast System Call)
LAHF-SAHF	lahf_lm (LAHF/SAHF in Long Mode)
DE	de (Debugging Extensions)
DTES64	Not directly listed in List 2.
DS	Not directly listed in List 2.
PCID	pcid (Process Context Identifiers)
INVPCID	invpcid (Invalidate Process Context Identifier)
PDCM	Not directly listed in List 2.
RDTSCP	rdtscp (Read Time-Stamp Counter and Processor ID)
TSC	tsc (Time Stamp Counter)
TSC-DEADLINE	tsc_deadline_timer (TSC Deadline Timer)
TSC-INVARIANT	constant_tsc, nonstop_tsc, tsc_reliable (These flags collectively indicate an invariant TSC)
xTPR	Not directly listed in List 2.
EIST	Not directly listed in List 2 by this name.
ACPI	Not directly listed in List 2 as a CPU flag.
TM	Not directly listed in List 2 by this name.
TM2	Not directly listed in List 2 by this name.
APIC	apic (Advanced Programmable Interrupt Controller)
x2APIC	x2apic (x2 Advanced Programmable Interrupt Controller)
MCE	mce (Machine Check Exception)
MCA	mca (Machine Check Architecture)
PBE	Not directly listed in List 2.
PREFETCHW	3dnowprefetch (AMD 3DNow! prefetch extensions, which include PREFETCHW). Intel CPUs might list prefetchw separately; if so, it's missing from this specific List 2 snippet

How to add a Windows 11 guest that support the Windows 11 requirements on Windows 11 Hyper-V host?

If you try to setup Windows 11 guest on Windows 11 Hyper-V default template, you will found the error below during setup.

But since you are already in Windows 11 host, then your system should be supported Windows 11 system requirements. So, how to resolve this issue?

You just need to go to your virtual machine settings on Hyper-V, enable the TPM (Trusted Platform Module), then you are set to go on Windows 11 guest setup.

Intel 11th Generation CPU Instructions Available on Hyper-V

Below is list of CPU instructions available on Windows 11 Pro Host for an 11th Gen Intel processor using Sysinternals Coreinfo. 

Note: * should be available CPU Instruction, and - is not available.

HTT             *       Hyperthreading enabled
CET             *       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        *       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       *       Supports AVX-512 Foundation instructions
AVX-512-DQ      *       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   *       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      *       Supports AVX-512 conflict detection instructions
AVX-512-BW      *       Supports AVX-512 byte and word instructions
AVX-512-VL      *       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          *       Can write history of 64-bit branch addresses
DS              *       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages

EIST            *       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Below is a list of CPU instructions available on Hyper-V Windows 10 guest.

HTT             *       Hyperthreading enabled
CET             *       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        *       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       *       Supports AVX-512 Foundation instructions
AVX-512-DQ      *       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   *       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      *       Supports AVX-512 conflict detection instructions
AVX-512-BW      *       Supports AVX-512 byte and word instructions
AVX-512-VL      *       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         -       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

If we compare between both, the result will be like below. As you can see, most of the CPU Instructions not available to the guest are mainly important for the Host OS only, such as Debug, Monitor, and Power Management.

List of CPU Instructions not available on the guest.

MONITOR         -       Supports MONITOR and MWAIT instructions
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
PDCM            -       Supports Performance Capabilities MSR
xTPR            -       Supports disabling task priority messages
EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
PBE             -       Supports use of FERR#/PBE# pin

For Windows 11 Sandbox, strangely enough, the differences are slightly difference with Hyper-V guest.

HTT             *       Hyperthreading enabled
CET             *       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        *       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       *       Supports AVX-512 Foundation instructions
AVX-512-DQ      *       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   *       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      *       Supports AVX-512 conflict detection instructions
AVX-512-BW      *       Supports AVX-512 byte and word instructions
AVX-512-VL      *       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         -       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   -       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

For the information above, it seems like Hyper-V exposes almost all the important CPU Instructions to the guest OS without any configuration which is difference with VirtualBox such as what mentioned on the Stack Overflow link below on quite many users find it difficult to enable AVX CPU Instructions.

How to enable AVX / AVX2 in VirtualBox 6.1.16 with Ubuntu 20.04 64bit?